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橙盒科技在长期解密技术研究和破解过程中，以各类疑难IC解密、单片机低成本解密方案为重点科研项目，致力于为电子企业及工程师提供高效可靠、具备成本与价格竞争优势的解密方案。
Power Modes Hibernate
PSoC 5 devices have four different power modes, as shown in
Active is the main processing mode. Its functionality is config-
Table 6-2 and Table 6-3. The power modes allow a design to
urable. Each power controllable subsystem is enabled or
easily provide required functionality and processing power while
disabled by using separate power configuration template
simultaneously minimizing power consumption and maximizing
registers. In alternate active mode, fewer subsystems are
battery life in low power and portable devices.
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
PSoC 5 power modes, in order of decreasing power
optimized to provide timed sleep intervals and Real Time Clock
consumption are:
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only Active
from I/O pins. Figure 6-3 illustrates the allowable transitions Alternate Active
between power modes. Sleep
橙盒科技芯片解密咨询电话：0755- 82221641，82175584
咨询QQ：1258381957，1315031281
Email：chkeji@126.com <mailto:chkeji@126.com>
橙盒科技在长期解密技术研究和破解过程中，以各类疑难IC解密、单片机低成本解密方案为重点科研项目，致力于为电子企业及工程师提供高效可靠、具备成本与价格竞争优势的解密方案。
Power Modes Hibernate
PSoC 5 devices have four different power modes, as shown in
Active is the main processing mode. Its functionality is config-
Table 6-2 and Table 6-3. The power modes allow a design to
urable. Each power controllable subsystem is enabled or
easily provide required functionality and processing power while
disabled by using separate power configuration template
simultaneously minimizing power consumption and maximizing
registers. In alternate active mode, fewer subsystems are
battery life in low power and portable devices.
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
PSoC 5 power modes, in order of decreasing power
optimized to provide timed sleep intervals and Real Time Clock
consumption are:
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only Active
from I/O pins. Figure 6-3 illustrates the allowable transitions Alternate Active
between power modes. Sleep
