MC9S12B128芯片解密是FREESCALE系列单片机解密领域较疑难型解密芯片之一，也是近期橙盒芯片解密研究所在FREESCALE系列芯片解密技术研究中成功破解的典型芯片型号。随着我们对MC9S12B128芯片的成功破解，在MOTOROLA系列单片机解密领域的研究又步入新的研究阶段，后期我们还将有更多型号被成功破解，将为更多客户提供最优质可靠的解密服务。
下面我们将针对MC9S12B128芯片的主要特征做简单介绍，供广大的技术工程师及芯片解密客户参考借鉴，以方便其理解芯片的内部结构及其加解密性质，更好的进行技术分析。
如果客户有MC9S12B128芯片解密需求，请与橙盒芯片解密研究所联系
芯片解密咨询电话：0755- 82221641，82173585
咨询QQ：1357273089，994589503
Email：chkeji@126.com
MC9S12B128 Features
16-bit CPU12
- Upward compatible with M68HC11 instruction set
- Interrupt stacking and programmer’s model identical to M68HC11
- 20-bit ALU
- Instruction queue
- Enhanced indexed addressing
Multiplexed bus
- Single chip or expanded
- 16 address/16 data wide or 16 address/8 data narrow modes
- External address space 1MByte for Data and Program space (112 pin package only)
Wake-up interrupt inputs depending on the package option
- 8-bit port H
- 4-bit port J
- 8-bit port P shared with PWM
Memory options
- 64K, 128K, 256K Byte Flash EEPROM
- 1K, 2K Byte EEPROM
- 2K, 4K and 8K Byte RAM
Analog-to-Digital Converter
- 16-channels for 112 Pin Package, 8 channels for 80 Pin package options, 10-bit resolution
- External conversion trigger capability
1M bit per second, CAN 2.0 A, B software compatible module
- Five receive and three transmit buffers
- Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
- Four separate interrupt channels for Rx, Tx, error and wake-up
- Low-pass filter wake-up function
- Loop-back for self test operation
Input Capture/Output Compare Timer (TIM)
- 16-bit Counter with 7-bit Prescaler
- 8 programmable input capture or output compare channels
- Simple PWM Mode
- Modulo Reset of Timer Counter
- 16-bit Pulse Accumulator
- External Event Counting
- Gated Time Accumulation
8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages)
- 8-bit 8-channel or 16-bit 4-channel
- Separate control for each pulse width and duty cycle
- Center- or left-aligned outputs
- Programmable clock select logic with a wide range of frequencies
Serial interfaces
- Two asynchronous serial communications interfaces (SCI)
- synchronous serial peripheral interface (SPI)
Inter-IC Bus (IIC)
- Compatible with I2C Bus standard
- Multi-master operation
- Software programmable for one of 256 different serial clock frequencies
SIM (System Integration Module)
- CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset)
- MEBI (multiplexed external bus interface)
- MMC (memory map and interface)
- INT (interrupt control)
- BKP (breakpoints)
- BDM (background debug mode)
Clock generation
- Phase-locked loop clock frequency multiplier
- Limp home mode in absence of external clock
- Clock Monitor
- Low power 0.5 to 16 MHz crystal oscillator reference clock
Operation frequency
- 32MHz equivalent to 16MHz Bus Speed for single chip
- 32MHz equivalent to 16MHz Bus Speed in expanded bus modes
- Option: 50MHz equivalent to 25Mhz Bus Speed
Internal 5V to 2.5V Regulator
112-Pin or 80-Pin LQFP package
- I/O lines with 5V input and drive capability
- 5VA/D converter inputs
- Dual supply - 5V for I/O and A/D, 2.5V logic
Development support
- Single-wire background debug? mode (BDM)
- On-chip hardware breakpoints
下面我们将针对MC9S12B128芯片的主要特征做简单介绍，供广大的技术工程师及芯片解密客户参考借鉴，以方便其理解芯片的内部结构及其加解密性质，更好的进行技术分析。
如果客户有MC9S12B128芯片解密需求，请与橙盒芯片解密研究所联系
芯片解密咨询电话：0755- 82221641，82173585
咨询QQ：1357273089，994589503
Email：chkeji@126.com
MC9S12B128 Features
16-bit CPU12
- Upward compatible with M68HC11 instruction set
- Interrupt stacking and programmer’s model identical to M68HC11
- 20-bit ALU
- Instruction queue
- Enhanced indexed addressing
Multiplexed bus
- Single chip or expanded
- 16 address/16 data wide or 16 address/8 data narrow modes
- External address space 1MByte for Data and Program space (112 pin package only)
Wake-up interrupt inputs depending on the package option
- 8-bit port H
- 4-bit port J
- 8-bit port P shared with PWM
Memory options
- 64K, 128K, 256K Byte Flash EEPROM
- 1K, 2K Byte EEPROM
- 2K, 4K and 8K Byte RAM
Analog-to-Digital Converter
- 16-channels for 112 Pin Package, 8 channels for 80 Pin package options, 10-bit resolution
- External conversion trigger capability
1M bit per second, CAN 2.0 A, B software compatible module
- Five receive and three transmit buffers
- Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
- Four separate interrupt channels for Rx, Tx, error and wake-up
- Low-pass filter wake-up function
- Loop-back for self test operation
Input Capture/Output Compare Timer (TIM)
- 16-bit Counter with 7-bit Prescaler
- 8 programmable input capture or output compare channels
- Simple PWM Mode
- Modulo Reset of Timer Counter
- 16-bit Pulse Accumulator
- External Event Counting
- Gated Time Accumulation
8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages)
- 8-bit 8-channel or 16-bit 4-channel
- Separate control for each pulse width and duty cycle
- Center- or left-aligned outputs
- Programmable clock select logic with a wide range of frequencies
Serial interfaces
- Two asynchronous serial communications interfaces (SCI)
- synchronous serial peripheral interface (SPI)
Inter-IC Bus (IIC)
- Compatible with I2C Bus standard
- Multi-master operation
- Software programmable for one of 256 different serial clock frequencies
SIM (System Integration Module)
- CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset)
- MEBI (multiplexed external bus interface)
- MMC (memory map and interface)
- INT (interrupt control)
- BKP (breakpoints)
- BDM (background debug mode)
Clock generation
- Phase-locked loop clock frequency multiplier
- Limp home mode in absence of external clock
- Clock Monitor
- Low power 0.5 to 16 MHz crystal oscillator reference clock
Operation frequency
- 32MHz equivalent to 16MHz Bus Speed for single chip
- 32MHz equivalent to 16MHz Bus Speed in expanded bus modes
- Option: 50MHz equivalent to 25Mhz Bus Speed
Internal 5V to 2.5V Regulator
112-Pin or 80-Pin LQFP package
- I/O lines with 5V input and drive capability
- 5VA/D converter inputs
- Dual supply - 5V for I/O and A/D, 2.5V logic
Development support
- Single-wire background debug? mode (BDM)
- On-chip hardware breakpoints
