橙盒科技专业承接EP20K30E 解密等ALTERA系列PLD/FPGA/CPLD芯片解密项目，承诺为广大客户提供高效、高可靠性、低成本、短周期的IC解密、单片机解密、DSP解密、专用IC解密、疑难IC解密等技术服务。
有EP20K30E 解密需求者请与橙盒科技联系
芯片解密咨询电话：0755- 82221641，82173585
咨询QQ：1357273089，994589503
Email：chkeji@126.com
EP20K30E Feature：
■Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration
- MultiCoreTM architecture integrating look-up table (LUT) logic,product-term logic, and embedded memory
- LUT logic used for register-intensive functions
- Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)
- ESB implementation of product-term logic used for combinatorial-intensive functions
■ High density
- 30,000 to 1.5 million typical gates (see Tables 1 and 2)
- Up to 51,840 logic elements (LEs)
- Up to 442,368 RAM bits that can be used without reducing available logic
- Up to 3,456 product-term-based macrocells
■ Designed for low-power operation
- 1.8-V and 2.5-V supply voltage (see Table 3)
- MultiVoltTM I/O interface support to interface with 1.8-V, 2.5-V,3.3-V, and 5.0-V devices (see Table 3)
- ESB offering programmable power-saving mode
■ Flexible clock management circuitry with up to four phase-locked loops (PLLs)
- Built-in low-skew clock tree
- Up to eight global clock signals
- ClockLock? feature reducing clock delay and skew
- ClockBoost? feature providing clock multiplication and division
- ClockShiftTM programmable clock phase and delay shifting
■ Powerful I/O features
- Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification,Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
- Support for high-speed external memories, including DDR SDRAM and ZBT SRAM (ZBT is a trademark of Integrated Device Technology, Inc.)
- Bidirectional I/O performance (tCO + tSU) up to 250 MHz
- LVDS performance up to 840 Mbits per channel
- Direct connection from I/O pins to local interconnect providing fast tCO and tSU times for complex logic
- MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,3.3-V, and 5.0-V devices (see Table 3)
- Programmable clamp to VCCIO
- Individual tri-state output enable control for each pin
- Programmable output slew-rate control to reduce switching noise
- Support for advanced I/O standards, including low-voltage differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stubseries terminated logic (SSTL-3 and SSTL-2), Gunning transceiver logic plus (GTL+), and high-speed terminated logic (HSTL Class I)
- Pull-up on I/O pins before and during configuration
■ Advanced interconnect structure
- Four-level hierarchical FastTrack? Interconnect structure providing fast, predictable interconnect delays
- Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions)
- Dedicated cascade chain that implements high-speed,high-fan-in logic functions (automatically used by software tools and megafunctions)
- Interleaved local interconnect allows one LE to drive 29 other LEs through the fast local interconnect
■ Advanced packaging options
- Available in a variety of packages with 144 to 1,020 pins (see Tables 4 through 7)
- FineLine BGA? packages maximize board space efficiency
■ Advanced software support
- Software design support and automatic place-and-route provided by the Altera? Quartus? II development system for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations
- Altera MegaCore? functions and Altera Megafunction Partners Program (AMPPSM) megafunctions
- NativeLinkTM integration with popular synthesis, simulation,and timing analysis tools
- Quartus II SignalTap? embedded logic analyzer simplifies in-system design evaluation by giving access to internal nodes during device operation
- Supports popular revision-control software packages including PVCS, Revision Control System (RCS), and Source Code Control System (SCCS )
