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TMS320LF2402解密——DSP解密

    有TMS320LF2402解密等TI系列DSP芯片解密需求者欢迎与橙盒芯片解密研究所联系咨询更多解密详情。这里,我们仅提供对TMS320LF2402芯片的主要功能特征介绍,供客户及解密工程师在解密项目合作中进行技术参考和分析。
    TMS320LF2402 FEATURES
  High-Performance Static CMOS Technology
  33-ns Instruction Cycle Time (30 MHz)
  30-MIPS Performance
  Low-Power 3.3-V Design
  Based on TMS320C2xx DSP CPU Core
  Code-Compatible With F243/F241/C242
  Instruction Set and Module Compatible With F240/C240
  On-Chip Memory
  Up to 32K Words x 16 Bits of Flash EEPROM (4 Sectors)
  Up to 2.5K Words x 16 Bits of Data/Program RAM
  544 Words of Dual-Access RAM
  Up to 2K Words of Single-Access RAM
  Boot ROM
  SCI/SPI Bootloader
  Two Event-Manager (EV) Modules (EVA and EVB), Each Include:
  Two 16-Bit General-Purpose Timers
  Eight 16-Bit Pulse-Width Modulation(PWM) Channels Which Enable:
  Three-Phase Inverter Control
  Center- or Edge-Alignment of PWM Channels
  Emergency PWM Channel Shutdown With External PDPINTx Pin
  Programmable Deadband (Deadtime)Prevents Shoot-Through Faults
  Three Capture Units For Time-Stamping of External Events
  On-Chip Position Encoder Interface Circuitry
  Synchronized Analog-to-Digital Conversion
  Designed for AC Induction, BLDC,Switched Reluctance, and Stepper Motor Control
  Applicable for Multiple Motor and/or Converter Control
  External Memory Interface (LF2407)
  192K Words x 16 Bits of Total Memory:64K Program, 64K Data, 64K I/O
  Watchdog (WD) Timer Module
  10-Bit Analog-to-Digital Converter (ADC)
  8 or 16 Multiplexed Input Channels
  500 ns Minimum Conversion Time
  Selectable Twin 8-Input Sequencers Triggered by Two Event Managers
  Controller Area Network (CAN) 2.0B Module
  Serial Communications Interface (SCI)
  16-Bit Serial Peripheral Interface (SPI)Module
  Phase-Locked-Loop (PLL)-Based Clock Generation
  Up to 40 Individually Programmable,Multiplexed General-Purpose Input/Output(GPIO) Pins
  Up to Five External Interrupts (Power Drive Protection, Reset, and Two Maskable Interrupts)
  Power Management:
  Three Power-Down Modes
  Ability to Power Down Each Peripheral Independently
  Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1? (JTAG)
  Development Tools Include:
  Texas Instruments (TI) ANSI C Compiler,Assembler/Linker, and Code Composer Studio? Debugger
  Evaluation Modules
  Scan-Based Self-Emulation (XDS510?)
  Broad Third-Party Digital Motor Control Support
  Package Options
  144-Pin Low-Profile Quad Flatpack(LQFP) PGE (LF2407)
  100-Pin LQFP PZ (LF2406)
  64-Pin Quad Flatpack (QFP) PG (LF2402)
  Extended Temperature Options (A and S)
  A: 40°C to 85°C
  S: 40°C to 125°C
    TMS320LF2402解密等TI系列DSP芯片解密请咨询
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[来源:芯片解密研究所] [作者:admin] [日期:09-11-24] [热度:]
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