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关于XC9536XL芯片
The XC9536XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of two 54V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns.
XC9536XL Features
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
36 macrocells with 800 usable gates
Available in small footprint packages -44-pin PLCC (34 user I/O pins) -44-pin VQFP (34 user I/O pins) -48-pin CSP (36 user I/O pins) -64-pin VQFP (36 user I/O pins) Optimized for high-performance 3.3V systems -Low power operation -5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals -3.3V or 2.5V output capability -Advanced 0.35 micron feature size CMOS FastFLASH? technology
Advanced system features -In-system programmable -Superior pin-locking and routability with FastCONNECT II? switch matrix -Extra wide 54-input Function Blocks -Up to 90 product-terms per macrocell with individual product-term allocation -Local clock inversion with three global and one product-term clocks -Individual output enable per output pin -Input hysteresis on all user and boundary-scan pin inputs -Bus-hold circuitry on all user pin inputs -Full IEEE Standard 1149.1 boundary-scan (JTAG).
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability -Endurance exceeding 10,000 program/erase cycles -20 year data retention -ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC9536 device in the 44-pin PLCC package and the 48-pin CSP package.
